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| author | Ivan Klokov <ivan.klokov@syntacore.com> | 2023-02-17 18:14:59 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-05 12:43:38 -0800 |
| commit | 270629024df1f9f4e704ce8325f958858c5cbff7 (patch) | |
| tree | 55a7ed05e9b5aced1ebfa263a0bb247ab0ab6d0f | |
| parent | 007698632814b4b4aeae1a9c176d932951e9c8cf (diff) | |
| download | focaccia-qemu-270629024df1f9f4e704ce8325f958858c5cbff7.tar.gz focaccia-qemu-270629024df1f9f4e704ce8325f958858c5cbff7.zip | |
disas/riscv Fix ctzw disassemble
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230217151459.54649-1-ivan.klokov@syntacore.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | disas/riscv.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/disas/riscv.c b/disas/riscv.c index ddda687c13..54455aaaa8 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = { { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, - { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, |