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| author | Emilio G. Cota <cota@braap.org> | 2016-06-27 15:02:00 -0400 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2016-10-26 08:29:01 -0700 |
| commit | 2a5fe8ae145ef7a3ab480922116d27efcc97b85d (patch) | |
| tree | 1f6f113aa0ab9627c34a429ed5a7933b5bb3ce91 | |
| parent | 60e573462fcdb83aa1a41e66a9f31dc8a4364399 (diff) | |
| download | focaccia-qemu-2a5fe8ae145ef7a3ab480922116d27efcc97b85d.tar.gz focaccia-qemu-2a5fe8ae145ef7a3ab480922116d27efcc97b85d.zip | |
target-i386: emulate LOCK'ed NOT using atomic helper
[rth: Avoid qemu_load that's redundant with the atomic op.] Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1467054136-10430-15-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-i386/translate.c | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index 2f39dac49f..6d71564317 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4674,10 +4674,15 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, rm = (modrm & 7) | REX_B(s); op = (modrm >> 3) & 7; if (mod != 3) { - if (op == 0) + if (op == 0) { s->rip_offset = insn_const_size(ot); + } gen_lea_modrm(env, s, modrm); - gen_op_ld_v(s, ot, cpu_T0, cpu_A0); + /* For those below that handle locked memory, don't load here. */ + if (!(s->prefix & PREFIX_LOCK) + || op != 2) { + gen_op_ld_v(s, ot, cpu_T0, cpu_A0); + } } else { gen_op_mov_v_reg(ot, cpu_T0, rm); } @@ -4690,11 +4695,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, set_cc_op(s, CC_OP_LOGICB + ot); break; case 2: /* not */ - tcg_gen_not_tl(cpu_T0, cpu_T0); - if (mod != 3) { - gen_op_st_v(s, ot, cpu_T0, cpu_A0); + if (s->prefix & PREFIX_LOCK) { + if (mod == 3) { + goto illegal_op; + } + tcg_gen_movi_tl(cpu_T0, ~0); + tcg_gen_atomic_xor_fetch_tl(cpu_T0, cpu_A0, cpu_T0, + s->mem_index, ot | MO_LE); } else { - gen_op_mov_reg_v(ot, rm, cpu_T0); + tcg_gen_not_tl(cpu_T0, cpu_T0); + if (mod != 3) { + gen_op_st_v(s, ot, cpu_T0, cpu_A0); + } else { + gen_op_mov_reg_v(ot, rm, cpu_T0); + } } break; case 3: /* neg */ |