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| author | BALATON Zoltan via <qemu-ppc@nongnu.org> | 2021-01-03 02:09:33 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-01-06 11:09:59 +1100 |
| commit | 2d4c816a8dcfb0d38712c3ffed5f5fcaedd7fe40 (patch) | |
| tree | dfb6315cf8b59a76334a7dc0e841a4fab91a8150 | |
| parent | 2a9cf49598c65d117b53f72d895ac3c20a3027bc (diff) | |
| download | focaccia-qemu-2d4c816a8dcfb0d38712c3ffed5f5fcaedd7fe40.tar.gz focaccia-qemu-2d4c816a8dcfb0d38712c3ffed5f5fcaedd7fe40.zip | |
ppc440_pcix: Fix register write trace event
The trace event for pci_host_config_write() was also using the trace event for read. Add corresponding trace and correct this. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <a6c7dcf7153cc537123ed8ceac060f2f64a883cb.1609636173.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | hw/ppc/ppc440_pcix.c | 2 | ||||
| -rw-r--r-- | hw/ppc/trace-events | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c index eb1290ffc8..7829d3e556 100644 --- a/hw/ppc/ppc440_pcix.c +++ b/hw/ppc/ppc440_pcix.c @@ -169,7 +169,7 @@ static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr, { struct PPC440PCIXState *s = opaque; - trace_ppc440_pcix_reg_read(addr, val); + trace_ppc440_pcix_reg_write(addr, val, size); switch (addr) { case PCI_VENDOR_ID ... PCI_MAX_LAT: stl_le_p(s->dev->config + addr, val); diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 6d8d095aa2..1e91984526 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -96,3 +96,4 @@ ppc440_pcix_set_irq(int irq_num) "PCI irq %d" ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of size=0x%" PRIx64 " to CPU=0x%" PRIx64 ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 +ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32 |