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| author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2024-08-02 15:24:16 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-08-06 14:16:55 +1000 |
| commit | 30d24145da72dc3f64d9d720ac2befad28e1daa2 (patch) | |
| tree | 5e750f30c06c810bb5bd3c675ac2ab610cc11ee6 | |
| parent | b19bbf2cf11297e8c8efd5a048b9e533d8fdface (diff) | |
| download | focaccia-qemu-30d24145da72dc3f64d9d720ac2befad28e1daa2.tar.gz focaccia-qemu-30d24145da72dc3f64d9d720ac2befad28e1daa2.zip | |
target/riscv: Add MXLEN check for F/D/Q applies to zama16b
Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240802072417.659-3-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/insn_trans/trans_rvd.c.inc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 0ac42c3223..49682292b8 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -47,7 +47,11 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - if (ctx->cfg_ptr->ext_zama16b) { + /* + * Zama16b applies to loads and stores of no more than MXLEN bits defined + * in the F, D, and Q extensions. + */ + if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { memop |= MO_ATOM_WITHIN16; } @@ -67,7 +71,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - if (ctx->cfg_ptr->ext_zama16b) { + if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { memop |= MO_ATOM_WITHIN16; } |