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| author | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2011-08-30 00:44:28 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2011-09-06 11:09:39 +0200 |
| commit | 344eecf6995f4a0ad1d887cec922f6806f91a3f8 (patch) | |
| tree | 485c3c2a48e6d112d158c8eaf0357dd59d82851b | |
| parent | c4cb2578b5d68716b6644edd69d25a1457607053 (diff) | |
| download | focaccia-qemu-344eecf6995f4a0ad1d887cec922f6806f91a3f8.tar.gz focaccia-qemu-344eecf6995f4a0ad1d887cec922f6806f91a3f8.zip | |
mips: Support the MT TCStatus IXMT irq disable flag
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
| -rw-r--r-- | target-mips/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index f6f16a34be..79e25583ff 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -537,6 +537,10 @@ static inline int cpu_mips_hw_interrupts_pending(CPUState *env) if (!(env->CP0_Status & (1 << CP0St_IE)) || (env->CP0_Status & (1 << CP0St_EXL)) || (env->CP0_Status & (1 << CP0St_ERL)) || + /* Note that the TCStatus IXMT field is initialized to zero, + and only MT capable cores can set it to one. So we don't + need to check for MT capabilities here. */ + (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) || (env->hflags & MIPS_HFLAG_DM)) { /* Interrupts are disabled */ return 0; |