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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-08-25 17:31:30 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:59:00 -0700 |
| commit | 3e0e41ef33a841bdefaaf2fd9224fd791da9d2c6 (patch) | |
| tree | bd4cfcf51083e824012b1cb5d38638f87df9b9f9 | |
| parent | a465772eea8fef59bef9a9fe424b1af4866991f5 (diff) | |
| download | focaccia-qemu-3e0e41ef33a841bdefaaf2fd9224fd791da9d2c6.tar.gz focaccia-qemu-3e0e41ef33a841bdefaaf2fd9224fd791da9d2c6.zip | |
target/openrisc: Implement l.adrp
This was added to the 1.3 spec. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/openrisc/disas.c | 1 | ||||
| -rw-r--r-- | target/openrisc/insns.decode | 2 | ||||
| -rw-r--r-- | target/openrisc/translate.c | 13 |
3 files changed, 16 insertions, 0 deletions
diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c index e51cbb24c6..ce112640b9 100644 --- a/target/openrisc/disas.c +++ b/target/openrisc/disas.c @@ -98,6 +98,7 @@ INSN(sw, "%d(r%d), r%d", a->i, a->a, a->b) INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b) INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b) INSN(nop, "") +INSN(adrp, "r%d, %d", a->d, a->i) INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i) INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i) INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i) diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 71e0d740db..0d6f7c29f8 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -102,6 +102,8 @@ l_maci 010011 ----- a:5 i:s16 l_movhi 000110 d:5 ----0 k:16 l_macrc 000110 d:5 ----1 00000000 00000000 +l_adrp 000010 d:5 i:s21 + #### # Arithmetic Instructions #### diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 6e8bc23568..6addbac8d6 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -799,6 +799,19 @@ static bool trans_l_nop(DisasContext *dc, arg_l_nop *a) return true; } +static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a) +{ + if (!check_v1_3(dc)) { + return false; + } + check_r0_write(dc, a->d); + + tcg_gen_movi_i32(cpu_R(dc, a->d), + (dc->base.pc_next & TARGET_PAGE_MASK) + + ((target_long)a->i << TARGET_PAGE_BITS)); + return true; +} + static bool trans_l_addi(DisasContext *dc, arg_rri *a) { TCGv t0; |