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| author | Tim 'mithro' Ansell <mithro@mithis.com> | 2017-04-18 16:15:51 +1000 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-04-21 23:56:00 +0900 |
| commit | 3fee028d1ea02cd16470dc5c65d54974ef85b673 (patch) | |
| tree | a3c5ffc541f87d3ca753306e83d7999bb23fc2a8 | |
| parent | 356a2db3c6f84e8e79e5afa3913514184bff5f50 (diff) | |
| download | focaccia-qemu-3fee028d1ea02cd16470dc5c65d54974ef85b673.tar.gz focaccia-qemu-3fee028d1ea02cd16470dc5c65d54974ef85b673.zip | |
target/openrisc: Implement EPH bit
Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
| -rw-r--r-- | target/openrisc/interrupt.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 78f0ba9421..2c91fab380 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |= env->evbar; } + if (env->sr & SR_EPH) { + vect_pc |= 0xf0000000; + } env->pc = vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |