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| author | Richard Henderson <rth@twiddle.net> | 2016-12-27 14:59:24 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-12-27 14:59:24 +0000 |
| commit | 416d72b97b01d6cb769ad0fd0e10614583354a45 (patch) | |
| tree | 272407530bf562692167eaab26e6525734bc8fc4 | |
| parent | 0f1944735b6bac810b067e8a7a5154744536fd59 (diff) | |
| download | focaccia-qemu-416d72b97b01d6cb769ad0fd0e10614583354a45.tar.gz focaccia-qemu-416d72b97b01d6cb769ad0fd0e10614583354a45.zip | |
target-arm: Fix aarch64 vec_reg_offset
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used for a big-endian host doesn't do what's intended. Fix this by adding in the vfp.regs offset after computing the inter-register offset. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-2-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/translate-a64.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6dc27a6115..ef7601b5e6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -527,7 +527,7 @@ static inline void assert_fp_access_checked(DisasContext *s) static inline int vec_reg_offset(DisasContext *s, int regno, int element, TCGMemOp size) { - int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); + int offs = 0; #ifdef HOST_WORDS_BIGENDIAN /* This is complicated slightly because vfp.regs[2n] is * still the low half and vfp.regs[2n+1] the high half @@ -540,6 +540,7 @@ static inline int vec_reg_offset(DisasContext *s, int regno, #else offs += element * (1 << size); #endif + offs += offsetof(CPUARMState, vfp.regs[regno * 2]); assert_fp_access_checked(s); return offs; } |