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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:02:46 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:46:26 -0800 |
| commit | 45b4dc8b403aa5473ec015336adf7d14d88e85c5 (patch) | |
| tree | 3649e7892b152f3d2a96ea9d53aca86e4c60d9ca | |
| parent | 29409c1d921d607873268671bf11a088efb5558e (diff) | |
| download | focaccia-qemu-45b4dc8b403aa5473ec015336adf7d14d88e85c5.tar.gz focaccia-qemu-45b4dc8b403aa5473ec015336adf7d14d88e85c5.zip | |
target/riscv: Mark both sstatus and msstatus_hs as dirty
Mark both sstatus and vsstatus as dirty (3). Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
| -rw-r--r-- | target/riscv/translate.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index eff064dc44..3ce86adb89 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -44,6 +44,8 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; + bool virt_enabled; + uint32_t opcode; uint32_t mstatus_fs; uint32_t misa; uint32_t mem_idx; @@ -395,6 +397,12 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + } tcg_temp_free(tmp); } #else @@ -742,6 +750,11 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->priv_ver = env->priv_ver; +#if !defined(CONFIG_USER_ONLY) + ctx->virt_enabled = riscv_cpu_virt_enabled(env); +#else + ctx->virt_enabled = false; +#endif ctx->misa = env->misa; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; |