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| author | Mark Corbin <mark@dibsco.co.uk> | 2024-09-17 01:51:05 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-02 15:11:52 +1000 |
| commit | 5341bf6afe86895be900e1709b62f9d4af9f97d8 (patch) | |
| tree | bc24d2c70d8f8fc33069eb311527f4e6e3a0dfbe | |
| parent | 92c15617e148b627a387e9cee2c2d8f807c7e246 (diff) | |
| download | focaccia-qemu-5341bf6afe86895be900e1709b62f9d4af9f97d8.tar.gz focaccia-qemu-5341bf6afe86895be900e1709b62f9d4af9f97d8.zip | |
bsd-user: Implement RISC-V CPU register cloning and reset functions
Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-4-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | bsd-user/riscv/target_arch_cpu.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index 9c31d9dc4c..a93ea3915a 100644 --- a/bsd-user/riscv/target_arch_cpu.h +++ b/bsd-user/riscv/target_arch_cpu.h @@ -131,4 +131,18 @@ static inline void target_cpu_loop(CPURISCVState *env) } } +static inline void target_cpu_clone_regs(CPURISCVState *env, target_ulong newsp) +{ + if (newsp) { + env->gpr[xSP] = newsp; + } + + env->gpr[xA0] = 0; + env->gpr[xT0] = 0; +} + +static inline void target_cpu_reset(CPUArchState *env) +{ +} + #endif /* TARGET_ARCH_CPU_H */ |