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| author | Shannon Zhao <shannon.zhao@linaro.org> | 2015-05-29 13:27:09 +0800 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2015-06-03 14:21:24 +0300 |
| commit | 5429273615e7b412402a7b22738737c09ab9f488 (patch) | |
| tree | 1f8d763eebc7e88a5c34ee90e0c48abcd1d90a74 | |
| parent | 2c85fad022a5c23b835d7c78b653763ae1e3f6eb (diff) | |
| download | focaccia-qemu-5429273615e7b412402a7b22738737c09ab9f488.tar.gz focaccia-qemu-5429273615e7b412402a7b22738737c09ab9f488.zip | |
hw/alpha/typhoon.c: Fix misusing qemu_allocate_irqs for single irq
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | hw/alpha/typhoon.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 7df842dff7..421162e1d4 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -841,7 +841,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, } } - *p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1); + *p_rtc_irq = qemu_allocate_irq(typhoon_set_timer_irq, s, 0); /* Main memory region, 0x00.0000.0000. Real hardware supports 32GB, but the address space hole reserved at this point is 8TB. */ @@ -918,11 +918,11 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, /* Init the ISA bus. */ /* ??? Technically there should be a cy82c693ub pci-isa bridge. */ { - qemu_irq isa_pci_irq, *isa_irqs; + qemu_irq *isa_irqs; *isa_bus = isa_bus_new(NULL, get_system_memory(), &s->pchip.reg_io); - isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1); - isa_irqs = i8259_init(*isa_bus, isa_pci_irq); + isa_irqs = i8259_init(*isa_bus, + qemu_allocate_irq(typhoon_set_isa_irq, s, 0)); isa_bus_irqs(*isa_bus, isa_irqs); } |