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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-09-05 18:53:50 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-09-24 10:29:43 -0700 |
| commit | 55b490b58fbfb4079186f05a1a63da1633239cbf (patch) | |
| tree | 2b054fe869696b8d674abf4e1edb0ac52540109e | |
| parent | 521c9e1b1adcbca90d1d84e1dc00ec63f17256ee (diff) | |
| download | focaccia-qemu-55b490b58fbfb4079186f05a1a63da1633239cbf.tar.gz focaccia-qemu-55b490b58fbfb4079186f05a1a63da1633239cbf.zip | |
target/riscv: Record misa_ext in TCGTBCPUState.cs_base
The tb_flush within write_misa was incorrect. It assumed that we could adjust the ISA of the current processor and discard all TB and all would be well. But MISA is per vcpu, so globally flushing TB does not mean that the TB matches the MISA of any given vcpu. By recording misa in the tb state, we ensure that the code generated matches the vcpu. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/riscv/csr.c | 3 | ||||
| -rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8842e07a73..3c8989f522 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -25,7 +25,6 @@ #include "pmu.h" #include "time_helper.h" #include "exec/cputlb.h" -#include "exec/tb-flush.h" #include "exec/icount.h" #include "accel/tcg/getpc.h" #include "qemu/guest-random.h" @@ -2173,8 +2172,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, env->mstatus &= ~MSTATUS_FS; } - /* flush translation cache */ - tb_flush(env_cpu(env)); env->xl = riscv_cpu_mxl(env); return RISCV_EXCP_NONE; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 78fb279184..143ab079d4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -191,7 +191,8 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) return (TCGTBCPUState){ .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc, - .flags = flags + .flags = flags, + .cs_base = env->misa_ext, }; } |