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| author | Anup Patel <apatel@ventanamicro.com> | 2022-06-28 15:47:35 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
| commit | 598ca8370634febb3438e7125278fd86b971a4a1 (patch) | |
| tree | f5eedec7ad07dd21cd8e9071ea09c0df8c6d655a | |
| parent | ec2c62dacc186893a6ce63089f96b1906dd68804 (diff) | |
| download | focaccia-qemu-598ca8370634febb3438e7125278fd86b971a4a1.tar.gz focaccia-qemu-598ca8370634febb3438e7125278fd86b971a4a1.zip | |
target/riscv: Set minumum priv spec version for mcountinhibit
The minimum priv spec versino for mcountinhibit to v1.11 so that it
is not available for v1.10 (or lower).
Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220628101737.786681-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d14a0cb0a0..4982e98735 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3944,7 +3944,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { write_mhpmcounter }, [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, - write_mcountinhibit }, + write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, write_mhpmevent }, |