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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-01-17 10:54:07 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-01-17 10:54:07 +0000 |
| commit | 5a15758874cfad886e637e015baa7888a0c60262 (patch) | |
| tree | 10d55e64394ecb01e19471ef155fefdbe87d6b02 | |
| parent | 8c4ec5c0269bda18bb777a64b2008088d1c632dc (diff) | |
| download | focaccia-qemu-5a15758874cfad886e637e015baa7888a0c60262.tar.gz focaccia-qemu-5a15758874cfad886e637e015baa7888a0c60262.zip | |
vexpress, realview: Add (dummy) L2 cache controller
Instantiate the L2 cache controller on the ARM devboards which have one, since we have a dummy model of it now. Note that the only non-MP board with an L2x0 is the PB1176, which we don't model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/realview.c | 2 | ||||
| -rw-r--r-- | hw/vexpress.c | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/hw/realview.c b/hw/realview.c index 3f35118f21..d2fde4426a 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -227,6 +227,8 @@ static void realview_init(ram_addr_t ram_size, for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } + sysbus_create_varargs("l2x0", realview_binfo.smp_priv_base + 0x2000, + NULL); } else { uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; /* For now just create the nIRQ GIC, and ignore the others. */ diff --git a/hw/vexpress.c b/hw/vexpress.c index 71115564e0..64fab4574c 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -182,6 +182,7 @@ static void vexpress_a9_init(ram_addr_t ram_size, /* 0x100ec000 TrustZone Address Space Controller */ /* 0x10200000 CoreSight debug APB */ /* 0x1e00a000 PL310 L2 Cache Controller */ + sysbus_create_varargs("l2x0", 0x1e00a000, NULL); /* CS0: NOR0 flash : 0x40000000 .. 0x44000000 */ /* CS4: NOR1 flash : 0x44000000 .. 0x48000000 */ |