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| author | Zhao Liu <zhao1.liu@intel.com> | 2025-07-14 16:08:59 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-07-14 10:29:17 +0200 |
| commit | 5d21ee453ad8e3f95f75e542cb3b35c5bb7cf23a (patch) | |
| tree | 6bbeb911a9537ca1313c8f9e75f00d57fd3a4c0a | |
| parent | 3e86124e7cb9b66e07fb992667865a308f16fcf2 (diff) | |
| download | focaccia-qemu-5d21ee453ad8e3f95f75e542cb3b35c5bb7cf23a.tar.gz focaccia-qemu-5d21ee453ad8e3f95f75e542cb3b35c5bb7cf23a.zip | |
i386/cpu: Honor maximum value for CPUID.8000001DH.EAX[25:14]
CPUID.8000001DH:EAX[25:14] is "NumSharingCache", and the number of logical processors sharing this cache is the value of this field incremented by 1. Because of its width limitation, the maximum value currently supported is 4095. Though at present Q35 supports up to 4096 CPUs, by constructing a specific topology, the width of the APIC ID can be extended beyond 12 bits. For example, using `-smp threads=33,cores=9,modules=9` results in a die level offset of 6 + 4 + 4 = 14 bits, which can also cause overflow. Check and honor the maximum value as CPUID.04H did. Cc: Babu Moger <babu.moger@amd.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250714080859.1960104-8-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fdc677614d..da7d8dca63 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -560,7 +560,8 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; + /* Bits 25:14 - NumSharingCache: maximum 4095. */ + *eax |= MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4095) << 14; assert(cache->line_size > 0); assert(cache->partitions > 0); |