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| author | Cathy Zhang <cathy.zhang@intel.com> | 2020-07-06 07:17:15 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-07-10 19:26:54 -0400 |
| commit | 5dd13f2a5b4d7335b2b0924e6fb28b63b34e70fe (patch) | |
| tree | b931a3bc3a6709df06b050912c1da9cd521313ed | |
| parent | 2f7057ac97579f940139ac85d8b757d47ef0efab (diff) | |
| download | focaccia-qemu-5dd13f2a5b4d7335b2b0924e6fb28b63b34e70fe.tar.gz focaccia-qemu-5dd13f2a5b4d7335b2b0924e6fb28b63b34e70fe.zip | |
target/i386: Add SERIALIZE cpu feature
The availability of the SERIALIZATION instruction is indicated by the presence of the CPUID feature flag SERIALIZE, which is defined as CPUID.(EAX=7,ECX=0):ECX[bit 14]. The release spec link is as follows: https://software.intel.com/content/dam/develop/public/us/en/documents/\ architecture-instruction-set-extensions-programming-reference.pdf The associated kvm patch link is as follows: https://lore.kernel.org/patchwork/patch/1268025/ Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Message-Id: <1593991036-12183-2-git-send-email-cathy.zhang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1dde34dce7..a05d3a641b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -986,7 +986,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", NULL, NULL, NULL, NULL, "avx512-vp2intersect", NULL, "md-clear", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, "serialize", NULL, NULL, NULL, NULL /* pconfig */, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9284f96896..bd71fe3ef2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -777,6 +777,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) +/* SERIALIZE instruction */ +#define CPUID_7_0_EDX_SERIALIZE (1U << 14) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ |