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| author | Philipp Kern <phil@philkern.de> | 2015-08-18 13:50:55 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2017-04-25 13:39:43 +0200 |
| commit | 601b9a9008c5a612d76073bb3f178621cff41980 (patch) | |
| tree | f87353784687559e187849a01c538239c2cad0e0 | |
| parent | f4b5b021c847669b1c78050aea26fe9abceef6dd (diff) | |
| download | focaccia-qemu-601b9a9008c5a612d76073bb3f178621cff41980.tar.gz focaccia-qemu-601b9a9008c5a612d76073bb3f178621cff41980.zip | |
target-s390x: Mask the SIGP order_code to 8bit.
According to "CPU Signaling and Response", "Signal-Processor Orders", the order field is bit position 56-63. Without this, the Linux guest kernel is sometimes unable to stop emulation and enters an infinite loop of "XXX unknown sigp: 0xffffffff00000005". Signed-off-by: Philipp Kern <phil@philkern.de> Reviewed-by: Thomas Huth <thuth@tuxfamily.org> [agraf: add comment according to email] Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target/s390x/misc_helper.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index 93b0e61366..83d38944d7 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -515,7 +515,8 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register" as parameter (input). Status (output) is always R1. */ - switch (order_code) { + /* sigp contains the order code in bit positions 56-63, mask it here. */ + switch (order_code & 0xff) { case SIGP_SET_ARCH: /* switch arch */ break; |