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| author | Max Filippov <jcmvbkbc@gmail.com> | 2020-05-04 05:15:14 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2020-05-17 14:52:25 -0700 |
| commit | 62ed68e33db89584355ca4c63cd5b21dd98df636 (patch) | |
| tree | 6e1d6515944c53fc28d396f516be7b892aa8b173 | |
| parent | 2cc2278edf0403720397a33b0747e0aba9e6d420 (diff) | |
| download | focaccia-qemu-62ed68e33db89584355ca4c63cd5b21dd98df636.tar.gz focaccia-qemu-62ed68e33db89584355ca4c63cd5b21dd98df636.zip | |
target/xtensa: fix simcall for newer hardware
After Xtensa release RE.2 simcall opcode has become nop for the hardware instead of illegal instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| -rw-r--r-- | target/xtensa/translate.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 546d2fa2fa..4bc15252c8 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2367,9 +2367,10 @@ static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[], #ifdef CONFIG_USER_ONLY bool ill = true; #else - bool ill = !semihosting_enabled(); + /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */ + bool ill = dc->config->hw_version <= 250002 && !semihosting_enabled(); #endif - if (ill) { + if (ill || !semihosting_enabled()) { qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); } return ill; @@ -2379,7 +2380,9 @@ static void translate_simcall(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_simcall(cpu_env); + if (semihosting_enabled()) { + gen_helper_simcall(cpu_env); + } #endif } |