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| author | Yongbok Kim <yongbok.kim@mips.com> | 2018-10-12 14:05:25 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | 630107955757b9dfc5c09f105caa267eded2e3b1 (patch) | |
| tree | b05658a480ad9246b71ad29a4d9e7a2ffe61e800 | |
| parent | 103be64c26c166f12b3e1308edadef3443723ff1 (diff) | |
| download | focaccia-qemu-630107955757b9dfc5c09f105caa267eded2e3b1.tar.gz focaccia-qemu-630107955757b9dfc5c09f105caa267eded2e3b1.zip | |
target/mips: Add reset state for PWSize and PWField registers
Add reset state for PWSize and PWField registers. The reset state is different for pre-R6 and R6 (and post-R6) ISAa. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| -rw-r--r-- | target/mips/translate.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 29a631aa83..159671cbb1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -26444,6 +26444,24 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Status |= (1 << CP0St_FR); } + if (env->insn_flags & ISA_MIPS32R6) { + /* PTW = 1 */ + env->CP0_PWSize = 0x40; + /* GDI = 12 */ + /* UDI = 12 */ + /* MDI = 12 */ + /* PRI = 12 */ + /* PTEI = 2 */ + env->CP0_PWField = 0x0C30C302; + } else { + /* GDI = 0 */ + /* UDI = 0 */ + /* MDI = 0 */ + /* PRI = 0 */ + /* PTEI = 2 */ + env->CP0_PWField = 0x02; + } + if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { /* microMIPS on reset when Config3.ISA is 3 */ env->hflags |= MIPS_HFLAG_M16; |