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authorSantiago Monserrat Campanello <santimonserr@gmail.com>2025-03-05 11:26:32 +0100
committerAlistair Francis <alistair.francis@wdc.com>2025-03-19 16:30:13 +1000
commit672cb29d1e811180bf1aeefbcb0936ecd5bd3853 (patch)
tree92b91f8aa5353fb6f5bab2e7a7fbb440dbd8e74b
parent1dae461a913f9da88df05de6e2020d3134356f2e (diff)
downloadfocaccia-qemu-672cb29d1e811180bf1aeefbcb0936ecd5bd3853.tar.gz
focaccia-qemu-672cb29d1e811180bf1aeefbcb0936ecd5bd3853.zip
docs/about/emulation: Fix broken link
semihosting link to risc-v changed

Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250305102632.91376-1-santimonserr@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r--docs/about/emulation.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst
index 3bc3579434..a72591ee4d 100644
--- a/docs/about/emulation.rst
+++ b/docs/about/emulation.rst
@@ -171,7 +171,7 @@ for that architecture.
     - Unified Hosting Interface (MD01069)
   * - RISC-V
     - System and User-mode
-    - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
+    - https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc
   * - Xtensa
     - System
     - Tensilica ISS SIMCALL