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authorPeter Maydell <peter.maydell@linaro.org>2018-11-02 13:16:13 +0000
committerPeter Maydell <peter.maydell@linaro.org>2018-11-02 13:16:13 +0000
commit69e2d03843412b9c076515b3aa9a71db161b6a1a (patch)
tree34a16e2a4c31b93f4af287c363951a87d1a45660
parentfbdd2b2b03cb42d6a1e54ae23199b7c2b401f898 (diff)
parenta094b3544f2855c0489f5df3c938b14b9a5899e5 (diff)
downloadfocaccia-qemu-69e2d03843412b9c076515b3aa9a71db161b6a1a.tar.gz
focaccia-qemu-69e2d03843412b9c076515b3aa9a71db161b6a1a.zip
Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf1' into staging
RISC-V Patches for the 3.1 Soft Freeze, Part 2

This tag contains a few simple patches that I'd like to target for the
QEMU soft freeze.  There's only one code change: a fix to our PMP
implementation that avoids an internal truncation while computing a
partial PMP read.

I also have two updates to the MAINTAINERS file: one to add Alistair as
a RISC-V maintainer, and one to add our newly created mailing list.

# gpg: Signature made Tue 30 Oct 2018 18:17:17 GMT
# gpg:                using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>"
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/riscv/tags/riscv-for-master-3.1-sf1:
  Add qemu-riscv@nongnu.org as the RISC-V list
  Add Alistair as a RISC-V Maintainer
  target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--MAINTAINERS2
-rw-r--r--target/riscv/pmp.c2
2 files changed, 3 insertions, 1 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index f2360efe3e..85f19f569f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -241,8 +241,10 @@ F: disas/ppc.c
 RISC-V
 M: Michael Clark <mjc@sifive.com>
 M: Palmer Dabbelt <palmer@sifive.com>
+M: Alistair Francis <Alistair.Francis@wdc.com>
 M: Sagar Karandikar <sagark@eecs.berkeley.edu>
 M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+L: qemu-riscv@nongnu.org
 S: Maintained
 F: target/riscv/
 F: hw/riscv/
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index f432f3b759..03abd8fe5e 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -325,7 +325,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
 {
     int i;
     target_ulong cfg_val = 0;
-    uint8_t val = 0;
+    target_ulong val = 0;
 
     for (i = 0; i < sizeof(target_ulong); i++) {
         val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);