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authorStefan Markovic <smarkovic@wavecomp.com>2018-08-02 16:16:26 +0200
committerAleksandar Markovic <amarkovic@wavecomp.com>2018-08-24 17:51:59 +0200
commit6d033ca7513d85562f1b6bbb002a38b1c2541e5d (patch)
tree88aa1416f4203d5b6ee7315b24e2fcda99077029
parent3285a3e4445be70d5f2dbdd29249e1e2627a5216 (diff)
downloadfocaccia-qemu-6d033ca7513d85562f1b6bbb002a38b1c2541e5d.tar.gz
focaccia-qemu-6d033ca7513d85562f1b6bbb002a38b1c2541e5d.zip
target/mips: Add emulation of DSP ASE for nanoMIPS - part 2
Add emulation of DSP ASE instructions for nanoMIPS - part 2.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
-rw-r--r--target/mips/translate.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d3635e71ba..59dcd87c67 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -19316,6 +19316,16 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 case NM_BC1NEZC:
                     gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
                     break;
+                case NM_BPOSGE32C:
+                    check_dspr2(ctx);
+                    {
+                        int32_t imm = extract32(ctx->opcode, 1, 13) |
+                                      extract32(ctx->opcode, 0, 1) << 13;
+
+                        gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2,
+                                              imm);
+                    }
+                    break;
                 default:
                     generate_exception_end(ctx, EXCP_RI);
                     break;