diff options
| author | Andrea Oliveri <oliveriandrea@gmail.com> | 2020-04-25 20:20:04 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> | 2020-06-09 17:32:45 +0200 |
| commit | 6db06115d246ea6d24755657a98c185ed2a50210 (patch) | |
| tree | fbef797dd631f2f2e6aa60769714b4b4b4bb169d | |
| parent | af868995e1b7641577300d1342ede452ef0c5565 (diff) | |
| download | focaccia-qemu-6db06115d246ea6d24755657a98c185ed2a50210.tar.gz focaccia-qemu-6db06115d246ea6d24755657a98c185ed2a50210.zip | |
target/mips: Enable hardware page table walker and CMGCR features for P5600
Enable hardware page table walker and CMGCR features for P5600 that supports both. Signed-off-by: Andrea Oliveri <oliveriandrea@gmail.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <de5adcb9fd0dd607b98026f4bfb34205432b6002.camel@gmail.com>
| -rw-r--r-- | target/mips/translate_init.inc.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index ffae10d4c4..637caccd89 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -366,7 +366,7 @@ const mips_def_t mips_defs[] = }, { /* FIXME: - * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL + * Config3: VZ, CTXTC, CDMM, TL * Config4: MMUExtDef * Config5: MRP * FIR(FCR0): Has2008 @@ -380,10 +380,11 @@ const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_FP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) | - (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | - (1 << CP0C3_VInt), + (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | + (1 << CP0C3_LPA) | (1 << CP0C3_VInt), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | (0x1c << CP0C4_KScrExist), .CP0_Config4_rw_bitmask = 0, |