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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-08-24 13:17:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-24 13:17:48 +0100 |
| commit | 6e0fafe2ef02378c696e7cf84ef41511e3b3b81a (patch) | |
| tree | 950ebecca49755605c2c63a6e8410f95a2ec4095 | |
| parent | 67aed15551f9814712d5ac25a155919b34fbd627 (diff) | |
| download | focaccia-qemu-6e0fafe2ef02378c696e7cf84ef41511e3b3b81a.tar.gz focaccia-qemu-6e0fafe2ef02378c696e7cf84ef41511e3b3b81a.zip | |
target/arm: Remove a handful of stray tabs
Following the bulk conversion of the iwMMXt code, there are just a handful of hard coded tabs in target/arm; fix them. This is a whitespace-only patch. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180821165215.29069-4-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/arm-semi.c | 2 | ||||
| -rw-r--r-- | target/arm/cpu.h | 16 |
2 files changed, 9 insertions, 9 deletions
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 7cac8734c7..b2b22d231e 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -136,7 +136,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) #ifdef CONFIG_USER_ONLY ts->swi_errno = err; #else - syscall_err = err; + syscall_err = err; #endif reg0 = ret; } else { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 62c36b4150..65c0fa0a65 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1320,14 +1320,14 @@ enum arm_cpu_mode { #define ARM_VFP_FPINST2 10 /* iwMMXt coprocessor control registers. */ -#define ARM_IWMMXT_wCID 0 -#define ARM_IWMMXT_wCon 1 -#define ARM_IWMMXT_wCSSF 2 -#define ARM_IWMMXT_wCASF 3 -#define ARM_IWMMXT_wCGR0 8 -#define ARM_IWMMXT_wCGR1 9 -#define ARM_IWMMXT_wCGR2 10 -#define ARM_IWMMXT_wCGR3 11 +#define ARM_IWMMXT_wCID 0 +#define ARM_IWMMXT_wCon 1 +#define ARM_IWMMXT_wCSSF 2 +#define ARM_IWMMXT_wCASF 3 +#define ARM_IWMMXT_wCGR0 8 +#define ARM_IWMMXT_wCGR1 9 +#define ARM_IWMMXT_wCGR2 10 +#define ARM_IWMMXT_wCGR3 11 /* V7M CCR bits */ FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) |