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| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2014-06-04 22:50:58 +1000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:44 +0200 |
| commit | 70c5340744f044d2195216d0e3c7c0c554dbd7ca (patch) | |
| tree | ad14cd30919b7cf760a4dc6b4b9d5946961e4738 | |
| parent | 45ed0be146b7433d1123f09eb1a984210a311625 (diff) | |
| download | focaccia-qemu-70c5340744f044d2195216d0e3c7c0c554dbd7ca.tar.gz focaccia-qemu-70c5340744f044d2195216d0e3c7c0c554dbd7ca.zip | |
target-ppc: Add POWER8's MMCR2/MMCRS SPRs
This adds POWER8 specific PMU MMCR2/MMCRS SPRs. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/cpu.h | 3 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 22 |
2 files changed, 25 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 6514edd992..d19e284061 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1476,6 +1476,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_MI_CTR (0x300) #define SPR_PERF1 (0x301) #define SPR_RCPU_MI_RBA1 (0x301) +#define SPR_POWER_UMMCR2 (0x301) #define SPR_PERF2 (0x302) #define SPR_RCPU_MI_RBA2 (0x302) #define SPR_MPC_MI_AP (0x302) @@ -1523,6 +1524,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_MD_TW (0x30F) #define SPR_UPERF0 (0x310) #define SPR_UPERF1 (0x311) +#define SPR_POWER_MMCR2 (0x311) #define SPR_UPERF2 (0x312) #define SPR_POWER_MMCRA (0X312) #define SPR_UPERF3 (0x313) @@ -1575,6 +1577,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_440_ITV3 (0x377) #define SPR_440_CCR1 (0x378) #define SPR_DCRIPR (0x37B) +#define SPR_POWER_MMCRS (0x37E) #define SPR_PPR (0x380) #define SPR_750_GQR0 (0x390) #define SPR_440_DNV0 (0x390) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 30ae66a27f..548b582542 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7507,6 +7507,26 @@ static void gen_spr_970_pmu_user(CPUPPCState *env) 0x00000000); } +static void gen_spr_power8_pmu_sup(CPUPPCState *env) +{ + spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCR2, 0x00000000); + spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCRS, 0x00000000); +} + +static void gen_spr_power8_pmu_user(CPUPPCState *env) +{ + spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); +} + static void gen_spr_power5p_ear(CPUPPCState *env) { /* External access control */ @@ -7673,6 +7693,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) gen_spr_power8_tce_address_control(env); gen_spr_power8_ids(env); gen_spr_power8_fscr(env); + gen_spr_power8_pmu_sup(env); + gen_spr_power8_pmu_user(env); } #if !defined(CONFIG_USER_ONLY) switch (version) { |