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| author | David Hildenbrand <dahi@linux.vnet.ibm.com> | 2014-09-30 10:57:32 +0200 |
|---|---|---|
| committer | Cornelia Huck <cornelia.huck@de.ibm.com> | 2014-10-10 10:37:47 +0200 |
| commit | 71dd7e69b30dc5024a8d891e7011173a81fe7a72 (patch) | |
| tree | a36e4673aeee855384f0a10f4dd87ff0c3b9eb36 | |
| parent | 99607144a423dd2cd3113587e36bc4dc65c4ddf1 (diff) | |
| download | focaccia-qemu-71dd7e69b30dc5024a8d891e7011173a81fe7a72.tar.gz focaccia-qemu-71dd7e69b30dc5024a8d891e7011173a81fe7a72.zip | |
s390x/kvm: synchronize the cpu state after SIGP (INITIAL) CPU RESET
We need to synchronize registers after a reset has been performed. The current code does that in qemu_system_reset(), load_normal_reset() and modified_clear_reset() for all vcpus. After SIGP (INITIAL) CPU RESET, this needs to be done for the targeted vcpu as well, so let's call cpu_synchronize_post_reset() in the respective handlers. Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> CC: Andreas Faerber <afaerber@suse.de> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
| -rw-r--r-- | target-s390x/kvm.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-s390x/kvm.c b/target-s390x/kvm.c index e4c4c8dc18..5b10a255ed 100644 --- a/target-s390x/kvm.c +++ b/target-s390x/kvm.c @@ -952,6 +952,7 @@ static void sigp_initial_cpu_reset(void *arg) cpu_synchronize_state(cpu); scc->initial_cpu_reset(cpu); + cpu_synchronize_post_reset(cpu); } static void sigp_cpu_reset(void *arg) @@ -961,6 +962,7 @@ static void sigp_cpu_reset(void *arg) cpu_synchronize_state(cpu); scc->cpu_reset(cpu); + cpu_synchronize_post_reset(cpu); } #define SIGP_ORDER_MASK 0x000000ff |