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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-07-15 17:28:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-07-15 17:28:59 +0100 |
| commit | 7692401a0826803522cfde533bdcc149932ddc6a (patch) | |
| tree | 22fb50a544350810105d024ad19820b9e45fe25f | |
| parent | 711dc6f36b74fe65a6e5a1847f1152717d887f8a (diff) | |
| parent | 76e2aef392629f2b2a468f5158d5c397cc5beed2 (diff) | |
| download | focaccia-qemu-7692401a0826803522cfde533bdcc149932ddc6a.tar.gz focaccia-qemu-7692401a0826803522cfde533bdcc149932ddc6a.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150715' into staging
target arm queue: * handle broken AArch64 kernels which assume DTB won't cross a 2MB boundary * correct broken SCTLR_EL3 reset value # gpg: Signature made Wed Jul 15 17:24:24 2015 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150715: hw/arm/boot: Increase fdt alignment target-arm: Fix broken SCTLR_EL3 reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/arm/boot.c | 28 | ||||
| -rw-r--r-- | target-arm/helper.c | 1 |
2 files changed, 23 insertions, 6 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index f48ed2d34d..5b969cda1c 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -735,12 +735,28 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) * we point to the kernel args. */ if (have_dtb(info)) { - /* Place the DTB after the initrd in memory. Note that some - * kernels will trash anything in the 4K page the initrd - * ends in, so make sure the DTB isn't caught up in that. - */ - hwaddr dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, - 4096); + hwaddr align; + hwaddr dtb_start; + + if (elf_machine == EM_AARCH64) { + /* + * Some AArch64 kernels on early bootup map the fdt region as + * + * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ] + * + * Let's play safe and prealign it to 2MB to give us some space. + */ + align = 2 * 1024 * 1024; + } else { + /* + * Some 32bit kernels will trash anything in the 4K page the + * initrd ends in, so make sure the DTB isn't caught up in that. + */ + align = 4096; + } + + /* Place the DTB after the initrd in memory with alignment. */ + dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); if (load_dtb(dtb_start, info, 0) < 0) { exit(1); } diff --git a/target-arm/helper.c b/target-arm/helper.c index b87afe7cde..01f0d0dac9 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2752,6 +2752,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write, .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) }, |