diff options
| author | Cathy Zhang <cathy.zhang@intel.com> | 2019-10-22 15:35:26 +0800 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2019-12-13 16:32:19 -0300 |
| commit | 77b168d221191156c47fcd8d1c47329dfdb9439e (patch) | |
| tree | 774f8e9547bcbe1a55cb549411a4c97421d563a2 | |
| parent | 4148d142a8cbbce10bb77e560997ae6b482e5edf (diff) | |
| download | focaccia-qemu-77b168d221191156c47fcd8d1c47329dfdb9439e.tar.gz focaccia-qemu-77b168d221191156c47fcd8d1c47329dfdb9439e.zip | |
i386: Add MSR feature bit for MDS-NO
Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow CPU models to report the feature when host supports it. Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Tao Xu <tao3.xu@intel.com> Message-Id: <1571729728-23284-2-git-send-email-cathy.zhang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| -rw-r--r-- | target/i386/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cde2a16b94..39d37e1225 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -838,6 +838,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define MSR_ARCH_CAP_RSBA (1U << 2) #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) #define MSR_ARCH_CAP_SSB_NO (1U << 4) +#define MSR_ARCH_CAP_MDS_NO (1U << 5) #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) |