diff options
| author | Fabien Chouteau <chouteau@adacore.com> | 2012-05-21 06:11:06 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-06-24 01:04:44 +0200 |
| commit | 77c2cf33fe8d272e5375b55c588202a18af0e27c (patch) | |
| tree | f7f5bb5d7e0cff6c717adddf7dc6db04caeb3715 | |
| parent | c8f803e77a39584af30082b7ba11e69a9f046224 (diff) | |
| download | focaccia-qemu-77c2cf33fe8d272e5375b55c588202a18af0e27c.tar.gz focaccia-qemu-77c2cf33fe8d272e5375b55c588202a18af0e27c.zip | |
booke_206_tlbwe: Discard invalid bits in MAS2
The size of EPN field in MAS2 depends on page size. This patch adds a mask to discard invalid bits in EPN field. Definition of EPN field from e500v2 RM: EPN Effective page number: Depending on page size, only the bits associated with a page boundary are valid. Bits that represent offsets within a page are ignored and should be cleared. There is a similar (but more complicated) definition in PowerISA V2.06. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/mmu_helper.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index d65d2909b4..c4e79d9ca7 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -3019,6 +3019,8 @@ void helper_booke206_tlbwe(CPUPPCState *env) uint32_t tlbncfg, tlbn; ppcmas_tlb_t *tlb; uint32_t size_tlb, size_ps; + target_ulong mask; + switch (env->spr[SPR_BOOKE_MAS0] & MAS0_WQ_MASK) { case MAS0_WQ_ALWAYS: @@ -3081,8 +3083,19 @@ void helper_booke206_tlbwe(CPUPPCState *env) tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12; } - /* XXX needs to change when supporting 64-bit e500 */ - tlb->mas2 = env->spr[SPR_BOOKE_MAS2] & 0xffffffff; + /* Make a mask from TLB size to discard invalid bits in EPN field */ + mask = ~(booke206_tlb_to_page_size(env, tlb) - 1); + /* Add a mask for page attributes */ + mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E; + + if (!msr_cm) { + /* Executing a tlbwe instruction in 32-bit mode will set + * bits 0:31 of the TLB EPN field to zero. + */ + mask &= 0xffffffff; + } + + tlb->mas2 = env->spr[SPR_BOOKE_MAS2] & mask; if (!(tlbncfg & TLBnCFG_IPROT)) { /* no IPROT supported by TLB */ |