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| author | Jim Shu <jim.shu@sifive.com> | 2025-09-24 15:48:17 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-10-03 13:15:14 +1000 |
| commit | 84c1605b7606d810ded4c1c3a2717f158dc89e3f (patch) | |
| tree | 86cc6b919bb301858654569b6ac7fd516c224ecc | |
| parent | c851052a77fd79300708df2070297b5428b4be8d (diff) | |
| download | focaccia-qemu-84c1605b7606d810ded4c1c3a2717f158dc89e3f.tar.gz focaccia-qemu-84c1605b7606d810ded4c1c3a2717f158dc89e3f.zip | |
target/riscv: Fix SSP CSR error handling in VU/VS mode
In VU/VS mode, accessing $ssp CSR will trigger the virtual instruction exception instead of illegal instruction exception if SSE is disabled via xenvcfg CSRs. This is from RISC-V CFI v1.0 spec ch2.2.4. Shadow Stack Pointer Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250924074818.230010-3-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3c8989f522..ea36eccb3d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -203,6 +203,8 @@ static RISCVException cfi_ss(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) if (env->debugger) { return RISCV_EXCP_NONE; + } else if (env->virt_enabled) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } #endif return RISCV_EXCP_ILLEGAL_INST; |