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| author | Glenn Miles <milesg@linux.ibm.com> | 2025-09-25 15:17:43 -0500 |
|---|---|---|
| committer | Harsh Prateek Bora <harshpb@linux.ibm.com> | 2025-09-28 23:26:52 +0530 |
| commit | 880aa4cb06ff5e86b6feab3030e14a16fea1dced (patch) | |
| tree | 8ae6c9149a16368f5818c99f23cdba0932a65426 | |
| parent | 7928680e0aaf0c755ce97800791bf73185749a88 (diff) | |
| download | focaccia-qemu-880aa4cb06ff5e86b6feab3030e14a16fea1dced.tar.gz focaccia-qemu-880aa4cb06ff5e86b6feab3030e14a16fea1dced.zip | |
target/ppc: Support for IBM PPE42 MMU
The IBM PPE42 processor only supports real mode addressing and does not distinguish between problem and supervisor states. It also uses the IR and DR MSR bits for other purposes. Therefore, add a check for PPE42 when we update hflags and cause it to ignore the IR and DR bits when calculating MMU indexes. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925201758.652077-6-milesg@linux.ibm.com Message-ID: <20250925201758.652077-6-milesg@linux.ibm.com>
| -rw-r--r-- | target/ppc/helper_regs.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 41b7b939ec..a07e6a7b7b 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -186,6 +186,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) if (env->spr[SPR_LPCR] & LPCR_HR) { hflags |= 1 << HFLAGS_HR; } + if (unlikely(ppc_flags & POWERPC_FLAG_PPE42)) { + /* PPE42 has a single address space and no problem state */ + msr = 0; + } #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { |