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| author | Greg Bellows <greg.bellows@linaro.org> | 2015-02-05 13:37:22 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-02-05 13:37:22 +0000 |
| commit | 884b4deeeb8b158ed3db5792161902bc8b41b62d (patch) | |
| tree | 0c90ab776f095a2d6bb8f9d3a53b983ab6f2c7fc | |
| parent | 5097227c15aa89baec1123aac25dd9500a62684d (diff) | |
| download | focaccia-qemu-884b4deeeb8b158ed3db5792161902bc8b41b62d.tar.gz focaccia-qemu-884b4deeeb8b158ed3db5792161902bc8b41b62d.zip | |
target-arm: Add missing SP_ELx register definition
Added CP register definitions for SP_EL1 and SP_EL2. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422029835-4696-5-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/helper.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 29f3b6277a..79c54a992e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .access = PL1_RW, .accessfn = sp_el0_access, .type = ARM_CP_NO_MIGRATE, .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, { .name = "SPSel", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_MIGRATE, @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), .resetvalue = 0 }, + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, REGINFO_SENTINEL }; |