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authorAlistair Francis <alistair.francis@wdc.com>2022-03-17 16:18:16 +1000
committerAlistair Francis <alistair.francis@wdc.com>2022-04-22 10:35:16 +1000
commit8b5c807bc07f8def162cbe7689eb1da4e80186ad (patch)
treed0039e1781525f43c8035d915e821a9d256726c3
parent7100fe6c2441741ca6fa7c28b8a372d8ff7c2953 (diff)
downloadfocaccia-qemu-8b5c807bc07f8def162cbe7689eb1da4e80186ad.tar.gz
focaccia-qemu-8b5c807bc07f8def162cbe7689eb1da4e80186ad.zip
target/riscv: cpu: Fixup indentation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220317061817.3856850-2-alistair.francis@opensource.wdc.com>
-rw-r--r--target/riscv/cpu.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c3fd018ecb..78fc7b22ed 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -569,18 +569,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
             error_setg(errp,
                        "I and E extensions are incompatible");
-                       return;
-       }
+            return;
+        }
 
         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
             error_setg(errp,
                        "Either I or E extension must be set");
-                       return;
-       }
+            return;
+        }
 
-       if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
-                               cpu->cfg.ext_a & cpu->cfg.ext_f &
-                               cpu->cfg.ext_d)) {
+        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
+                                cpu->cfg.ext_a & cpu->cfg.ext_f &
+                                cpu->cfg.ext_d)) {
             warn_report("Setting G will also set IMAFD");
             cpu->cfg.ext_i = true;
             cpu->cfg.ext_m = true;
@@ -711,11 +711,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
         case IRQ_S_EXT:
         case IRQ_VS_EXT:
         case IRQ_M_EXT:
-             if (kvm_enabled()) {
+            if (kvm_enabled()) {
                 kvm_riscv_set_irq(cpu, irq, level);
-             } else {
+            } else {
                 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
-             }
+            }
              break;
         default:
             g_assert_not_reached();