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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-26 15:21:24 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-06-13 17:38:08 +1000 |
| commit | 90b0aecaf9148cc3a78abee7deb824ca6cf13ad5 (patch) | |
| tree | 68664f9370fa000313ed056e75b3a62feeb60904 | |
| parent | 356c13f94dbff3f32e9d3615f6caa35a2a324d8d (diff) | |
| download | focaccia-qemu-90b0aecaf9148cc3a78abee7deb824ca6cf13ad5.tar.gz focaccia-qemu-90b0aecaf9148cc3a78abee7deb824ca6cf13ad5.zip | |
target/riscv: Remove pc_succ_insn from DisasContext
pc_succ_insn is no longer useful after the introduce of cur_insn_len and all pc related value use diff value instead of absolute value. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/translate.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index bd2da9b079..8a33da811e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -59,8 +59,6 @@ typedef enum { typedef struct DisasContext { DisasContextBase base; - /* pc_succ_insn points to the instruction following base.pc_next */ - target_ulong pc_succ_insn; target_ulong cur_insn_len; target_ulong pc_save; target_ulong priv_ver; @@ -1149,7 +1147,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) /* Check for compressed insn */ if (ctx->cur_insn_len == 2) { ctx->opcode = opcode; - ctx->pc_succ_insn = ctx->base.pc_next + 2; /* * The Zca extension is added as way to refer to instructions in the C * extension that do not include the floating-point loads and stores @@ -1164,7 +1161,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) translator_lduw(env, &ctx->base, ctx->base.pc_next + 2)); ctx->opcode = opcode32; - ctx->pc_succ_insn = ctx->base.pc_next + 4; for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { if (decoders[i].guard_func(ctx) && @@ -1185,7 +1181,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) uint32_t tb_flags = ctx->base.tb->flags; ctx->pc_save = ctx->base.pc_first; - ctx->pc_succ_insn = ctx->base.pc_first; ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); @@ -1238,7 +1233,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) ctx->ol = ctx->xl; decode_opc(env, ctx, opcode16); - ctx->base.pc_next = ctx->pc_succ_insn; + ctx->base.pc_next += ctx->cur_insn_len; /* Only the first insn within a TB is allowed to cross a page boundary. */ if (ctx->base.is_jmp == DISAS_NEXT) { |