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| author | Cédric Le Goater <clg@kaod.org> | 2022-01-12 11:28:26 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-12 11:28:26 +0100 |
| commit | 91137619c6555a3c7cdd829f3b91b6da2bf67475 (patch) | |
| tree | 8c69bb4d5f0433d2a1f850f3bae094e53596fb59 | |
| parent | 2460e1d75ba60ee67fadabccd988705b7bb911cd (diff) | |
| download | focaccia-qemu-91137619c6555a3c7cdd829f3b91b6da2bf67475.tar.gz focaccia-qemu-91137619c6555a3c7cdd829f3b91b6da2bf67475.zip | |
target/ppc: Add extra float instructions to POWER5P processors
ISA v2.03 introduced Floating Round to Integer instructions : frin, friz, frip, and frim. Add them to POWER5+. The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal Estimate) instruction which was introduced in ISA v2.0x. The architecture document says its optional and that might be the reason why it has been kept under the PPC_FLOAT_EXT flag. This means 970 CPUs can not use it under QEMU, which doesn't seem to be a problem. Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | target/ppc/cpu_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index f15a52259c..e30e86fe9d 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6953,6 +6953,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | |