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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-29 16:55:07 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-06-24 16:48:08 +0200 |
| commit | 916e957070e1f4b697c905d0a35984e70f106ed6 (patch) | |
| tree | 335e5da41f08e1b8146a70e3332d3e228eb8ce8b | |
| parent | 9f47eb54b25e67b28a85a0b3eac304f2909f10ae (diff) | |
| download | focaccia-qemu-916e957070e1f4b697c905d0a35984e70f106ed6.tar.gz focaccia-qemu-916e957070e1f4b697c905d0a35984e70f106ed6.zip | |
target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases
These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have
been added commit 3c824109da0 ("target-mips: microMIPS ASE support").
More than 11 years later it is safe to assume there won't be added
soon. The cases fall back to the default which generates a RESERVED
INSTRUCTION, so it is safe to remove them.
Functionally speaking, the patch is a no-op.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174323.2900831-8-f4bug@amsat.org>
| -rw-r--r-- | target/mips/tcg/translate.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 8b25118320..1ff0b098bc 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -14076,8 +14076,6 @@ enum { BGEZALS = 0x13, BC2F = 0x14, BC2T = 0x15, - BPOSGE64 = 0x1a, - BPOSGE32 = 0x1b, /* These overlap and are distinguished by bit16 of the instruction */ BC1F = 0x1c, BC1T = 0x1d, @@ -16121,10 +16119,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) generate_exception_err(ctx, EXCP_CpU, 1); } break; - case BPOSGE64: - case BPOSGE32: - /* MIPS DSP: not implemented */ - /* Fall through */ default: MIPS_INVAL("pool32i"); gen_reserved_instruction(ctx); |