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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-01-29 11:24:01 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-03-06 11:45:21 -0800 |
| commit | 9758c8cbbdeaefc4e065c7614a6d10c9db810c25 (patch) | |
| tree | 5df24b94eaf9eb9a28b4c45477664fe0dfa04789 | |
| parent | a7391bc0157bf20f41ff14dbf2ec66ec60cb633c (diff) | |
| download | focaccia-qemu-9758c8cbbdeaefc4e065c7614a6d10c9db810c25.tar.gz focaccia-qemu-9758c8cbbdeaefc4e065c7614a6d10c9db810c25.zip | |
tcg/tci: Remove tci_read_r8s
Use explicit casts for ext8s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/tci.c | 25 |
1 files changed, 4 insertions, 21 deletions
diff --git a/tcg/tci.c b/tcg/tci.c index 4ade0ccaf9..7325c8bfd0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int8_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { @@ -164,16 +157,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -/* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - int8_t value = tci_read_reg8s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} -#endif - /* Read indexed register (16 bit) from bytecode. */ static uint16_t tci_read_r16(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -695,8 +678,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 = *tb_ptr++; - t1 = tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 @@ -910,8 +893,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 = *tb_ptr++; - t1 = tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 |