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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-03-07 08:48:33 +0100 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2021-07-09 18:42:46 +0200 |
| commit | 9bb5405482e7be4c0a6f259d4f18ea612d4a31ba (patch) | |
| tree | a9cbd0bccdd5308c83b4aae42dae0ecd6f2c64e4 | |
| parent | 0849cb547844b7205af01455b82dc54956c978a9 (diff) | |
| download | focaccia-qemu-9bb5405482e7be4c0a6f259d4f18ea612d4a31ba.tar.gz focaccia-qemu-9bb5405482e7be4c0a6f259d4f18ea612d4a31ba.zip | |
memory: Display MemoryRegion name in read/write ops trace events
MemoryRegion names is cached on first call to memory_region_name(), so displaying the name is trace events is cheap. Add it for read / write ops. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210307074833.143106-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| -rw-r--r-- | softmmu/memory.c | 12 | ||||
| -rw-r--r-- | softmmu/trace-events | 4 |
2 files changed, 10 insertions, 6 deletions
diff --git a/softmmu/memory.c b/softmmu/memory.c index f0161515e9..24a97c8b1f 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -442,7 +442,8 @@ static MemTxResult memory_region_read_accessor(MemoryRegion *mr, trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); - trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); + trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size, + memory_region_name(mr)); } memory_region_shift_read_access(value, shift, mask, tmp); return MEMTX_OK; @@ -464,7 +465,8 @@ static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr, trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size); } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); - trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size); + trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size, + memory_region_name(mr)); } memory_region_shift_read_access(value, shift, mask, tmp); return r; @@ -484,7 +486,8 @@ static MemTxResult memory_region_write_accessor(MemoryRegion *mr, trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); - trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); + trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size, + memory_region_name(mr)); } mr->ops->write(mr->opaque, addr, tmp, size); return MEMTX_OK; @@ -504,7 +507,8 @@ static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr, trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size); } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) { hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr); - trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size); + trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size, + memory_region_name(mr)); } return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs); } diff --git a/softmmu/trace-events b/softmmu/trace-events index d18ac41e4e..7b278590a0 100644 --- a/softmmu/trace-events +++ b/softmmu/trace-events @@ -9,8 +9,8 @@ cpu_in(unsigned int addr, char size, unsigned int val) "addr 0x%x(%c) value %u" cpu_out(unsigned int addr, char size, unsigned int val) "addr 0x%x(%c) value %u" # memory.c -memory_region_ops_read(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" -memory_region_ops_write(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" +memory_region_ops_read(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size, const char *name) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u name '%s'" +memory_region_ops_write(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size, const char *name) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u name '%s'" memory_region_subpage_read(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_subpage_write(int cpu_index, void *mr, uint64_t offset, uint64_t value, unsigned size) "cpu %d mr %p offset 0x%"PRIx64" value 0x%"PRIx64" size %u" memory_region_ram_device_read(int cpu_index, void *mr, uint64_t addr, uint64_t value, unsigned size) "cpu %d mr %p addr 0x%"PRIx64" value 0x%"PRIx64" size %u" |