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authorBin Meng <bmeng@tinylab.org>2023-02-28 21:45:34 +0800
committerPalmer Dabbelt <palmer@rivosinc.com>2023-03-01 16:40:24 -0800
commit9e83a35661e76652dcbdd761b8a63649f93a3d38 (patch)
tree76e7e73e5391271fe5bc70422f4b2d66ea39cb57
parente4e1f216a1ece6a69d10b22bc6f1cf855e054c95 (diff)
downloadfocaccia-qemu-9e83a35661e76652dcbdd761b8a63649f93a3d38.tar.gz
focaccia-qemu-9e83a35661e76652dcbdd761b8a63649f93a3d38.zip
target/riscv: Drop priv level check in mseccfg predicate()
riscv_csrrw_check() already does the generic privilege level check
hence there is no need to do the specific M-mode access check in
the mseccfg predicate().

With this change debugger can access the mseccfg CSR anytime.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230228104035.1879882-18-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
-rw-r--r--target/riscv/csr.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 020c3f524f..785f6f4d45 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -451,7 +451,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
 
 static RISCVException epmp(CPURISCVState *env, int csrno)
 {
-    if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) {
+    if (riscv_cpu_cfg(env)->epmp) {
         return RISCV_EXCP_NONE;
     }