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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-05-15 11:56:09 +0900 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-05-24 10:38:50 +1000 |
| commit | 9f6b7da5d27b744ddbdba98ba8b89c710dd3c1b7 (patch) | |
| tree | 1e1da0fa2f39d675360770089cfdd5740850006c | |
| parent | 1d398ab9dcfb8f5fb4b9a285ea3167f7ba85976d (diff) | |
| download | focaccia-qemu-9f6b7da5d27b744ddbdba98ba8b89c710dd3c1b7.tar.gz focaccia-qemu-9f6b7da5d27b744ddbdba98ba8b89c710dd3c1b7.zip | |
target/riscv: Change "G" expansion
On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei". Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to be (virtually) enabled as well, it should be safe to change its expansion. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <d1b5be550a2893a0fd32c928f832d2ff7bfafe35.1652583332.git.research_trasio@irq.a4lg.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1fb76b4295..4ca6a8623f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -598,13 +598,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d)) { - warn_report("Setting G will also set IMAFD"); + cpu->cfg.ext_d && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i = true; cpu->cfg.ext_m = true; cpu->cfg.ext_a = true; cpu->cfg.ext_f = true; cpu->cfg.ext_d = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.ext_ifencei = true; } if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || |