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| author | Helge Deller <deller@gmx.de> | 2023-11-17 11:02:39 +0100 |
|---|---|---|
| committer | Helge Deller <deller@gmx.de> | 2023-11-17 18:36:36 +0100 |
| commit | a01491a238fab670ba68b5c649c109c64ae23e21 (patch) | |
| tree | c1fa68b3bdadc8a575f6c773e8d5aad54c0f7ca5 | |
| parent | 34a5cb6d8434303c170230644b2a7c1d5781d197 (diff) | |
| download | focaccia-qemu-a01491a238fab670ba68b5c649c109c64ae23e21.tar.gz focaccia-qemu-a01491a238fab670ba68b5c649c109c64ae23e21.zip | |
target/hppa: Fix 64-bit SHRPD instruction
When shifting the two joined 64-bit registers right, shift the upper 64-bit register to the left and the lower 64-bit register to the right before merging them with OR. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/hppa/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4a4830c3e3..3ef39b1bd7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3438,9 +3438,9 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) TCGv_i64 n = tcg_temp_new_i64(); tcg_gen_xori_i64(n, cpu_sar, 63); - tcg_gen_shl_i64(t, src2, n); + tcg_gen_shl_i64(t, src1, n); tcg_gen_shli_i64(t, t, 1); - tcg_gen_shr_i64(dest, src1, cpu_sar); + tcg_gen_shr_i64(dest, src2, cpu_sar); tcg_gen_or_i64(dest, dest, t); } else { TCGv_i64 t = tcg_temp_new_i64(); |