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| author | Pierrick Bouvier <pierrick.bouvier@linaro.org> | 2025-05-12 11:04:27 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-05-14 15:12:40 +0100 |
| commit | a0307ea3dde1089d764a4449b62815023a1abbc6 (patch) | |
| tree | b8c3e3cb3b02def45d4f309b5a0b8f994aa291d4 | |
| parent | 21a75f792f088d0aabebf6b7d96490e37fe8b779 (diff) | |
| download | focaccia-qemu-a0307ea3dde1089d764a4449b62815023a1abbc6.tar.gz focaccia-qemu-a0307ea3dde1089d764a4449b62815023a1abbc6.zip | |
target/arm/helper: use vaddr instead of target_ulong for exception_pc_alignment
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-14-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.h | 2 | ||||
| -rw-r--r-- | target/arm/tcg/tlb_helper.c | 2 | ||||
| -rw-r--r-- | target/arm/tcg/translate-a64.c | 2 | ||||
| -rw-r--r-- | target/arm/tcg/translate.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/target/arm/helper.h b/target/arm/helper.h index 0907505839..95b9211c6f 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -49,7 +49,7 @@ DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_swstep, noreturn, env, i32) -DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 5ea4d6590f..d9e6c827d4 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -276,7 +276,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } -void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +void helper_exception_pc_alignment(CPUARMState *env, vaddr pc) { ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; int target_el = exception_target_el(env); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 52cf47e775..ac80f572a2 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10242,7 +10242,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * start of the TB. */ assert(s->base.num_insns == 1); - gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_vaddr(pc)); s->base.is_jmp = DISAS_NORETURN; s->base.pc_next = QEMU_ALIGN_UP(pc, 4); return; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index e773ab7268..9962f43b1d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7791,7 +7791,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * be possible after an indirect branch, at the start of the TB. */ assert(dc->base.num_insns == 1); - gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_vaddr(pc)); dc->base.is_jmp = DISAS_NORETURN; dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); return; |