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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2018-04-13 09:46:28 +0200
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2018-05-29 09:33:40 +0200
commita17f7c05f07aa3a825f7dc1ba22d70df16098d3c (patch)
tree2ea5c8820633e42a7360b93743070c5049bb5fff
parentcfeea807e5af996979b2c13ab3b6eb447e1796bb (diff)
downloadfocaccia-qemu-a17f7c05f07aa3a825f7dc1ba22d70df16098d3c.tar.gz
focaccia-qemu-a17f7c05f07aa3a825f7dc1ba22d70df16098d3c.zip
target-microblaze: Remove USE_MMU PVR checks
We already have a CPU property to control if a core has
an MMU or not. Remove USE_MMU PVR checks in favor of
looking at the property.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-rw-r--r--target/microblaze/helper.c12
1 files changed, 1 insertions, 11 deletions
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 387d4aca5a..a9f4ca93e3 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -54,21 +54,11 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
     CPUMBState *env = &cpu->env;
     unsigned int hit;
-    unsigned int mmu_available;
     int r = 1;
     int prot;
 
-    mmu_available = 0;
-    if (cpu->cfg.use_mmu) {
-        mmu_available = 1;
-        if ((cpu->cfg.pvr == C_PVR_FULL) &&
-            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
-            mmu_available = 0;
-        }
-    }
-
     /* Translate if the MMU is available and enabled.  */
-    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
+    if (cpu->cfg.use_mmu && (env->sregs[SR_MSR] & MSR_VM)) {
         uint32_t vaddr, paddr;
         struct microblaze_mmu_lookup lu;