diff options
| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-08 19:29:54 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-08 19:29:54 +0000 |
| commit | a20e31dcf0260ced84729ebab39c0181ae1966d7 (patch) | |
| tree | 75c10b696de7203bc275e3d3ccf1772510ae1fd6 | |
| parent | 002bac8eaebbe99b2ff8706261b6fe16a59d0424 (diff) | |
| download | focaccia-qemu-a20e31dcf0260ced84729ebab39c0181ae1966d7.tar.gz focaccia-qemu-a20e31dcf0260ced84729ebab39c0181ae1966d7.zip | |
Use a common constant for temp_buf size
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4176 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | cpu-defs.h | 4 | ||||
| -rw-r--r-- | translate-all.c | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/cpu-defs.h b/cpu-defs.h index 6979c1145f..1591748d43 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -132,6 +132,7 @@ typedef struct CPUTLBEntry { sizeof(target_phys_addr_t))]; } CPUTLBEntry; +#define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ struct TranslationBlock *current_tb; /* currently executing TB */ \ /* soft mmu support */ \ @@ -145,7 +146,8 @@ typedef struct CPUTLBEntry { /* The meaning of the MMU modes is defined in the target code. */ \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ - long temp_buf[128]; /* buffer for temporaries in the code generator */ \ + /* buffer for temporaries in the code generator */ \ + long temp_buf[CPU_TEMP_BUF_NLONGS]; \ \ /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ diff --git a/translate-all.c b/translate-all.c index 061bb901a3..d16d218f3c 100644 --- a/translate-all.c +++ b/translate-all.c @@ -85,7 +85,7 @@ void cpu_gen_init(void) { tcg_context_init(&tcg_ctx); tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf), - 128 * sizeof(long)); + CPU_TEMP_BUF_NLONGS * sizeof(long)); } /* return non zero if the very first instruction is invalid so that |