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| author | David Hildenbrand <david@redhat.com> | 2019-03-07 13:15:33 +0100 |
|---|---|---|
| committer | Cornelia Huck <cohuck@redhat.com> | 2019-03-11 09:31:01 +0100 |
| commit | a2338cfb07536c1d3c19ab9b698cb9c3e2a58ea2 (patch) | |
| tree | 62ad953f0260b6177333d42a514ed51d5d6b5880 | |
| parent | db23070c7607301088ed2a3ef85bef0b3af80a30 (diff) | |
| download | focaccia-qemu-a2338cfb07536c1d3c19ab9b698cb9c3e2a58ea2.tar.gz focaccia-qemu-a2338cfb07536c1d3c19ab9b698cb9c3e2a58ea2.zip | |
s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
Load both elements signed and store them into the two 64 bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-27-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| -rw-r--r-- | target/s390x/insn-data.def | 2 | ||||
| -rw-r--r-- | target/s390x/translate_vx.inc.c | 33 |
2 files changed, 35 insertions, 0 deletions
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index ae58ff440b..555250fd5a 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1032,6 +1032,8 @@ E(0xe71a, VSCEG, VRV, V, la2, 0, 0, 0, vsce, 0, ES_64, IF_VEC) /* VECTOR SELECT */ F(0xe78d, VSEL, VRR_e, V, 0, 0, 0, 0, vsel, 0, IF_VEC) +/* VECTOR SIGN EXTEND TO DOUBLEWORD */ + F(0xe75f, VSEG, VRR_a, V, 0, 0, 0, 0, vseg, 0, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index e685506b8c..cf1d319e4e 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -784,3 +784,36 @@ static DisasJumpType op_vsel(DisasContext *s, DisasOps *o) get_field(s->fields, v3), get_field(s->fields, v4), &gvec_op); return DISAS_NEXT; } + +static DisasJumpType op_vseg(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s->fields, m3); + int idx1, idx2; + TCGv_i64 tmp; + + switch (es) { + case ES_8: + idx1 = 7; + idx2 = 15; + break; + case ES_16: + idx1 = 3; + idx2 = 7; + break; + case ES_32: + idx1 = 1; + idx2 = 3; + break; + default: + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + read_vec_element_i64(tmp, get_field(s->fields, v2), idx1, es | MO_SIGN); + write_vec_element_i64(tmp, get_field(s->fields, v1), 0, ES_64); + read_vec_element_i64(tmp, get_field(s->fields, v2), idx2, es | MO_SIGN); + write_vec_element_i64(tmp, get_field(s->fields, v1), 1, ES_64); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} |