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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2013-08-20 16:19:24 +0530 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-09-02 10:06:42 +0200 |
| commit | a3cedb541ca3ecc82040f597a4054419fdb22fa5 (patch) | |
| tree | df9a71292a22fcc630d9ea96035e19e5209356f4 | |
| parent | 5dac82ce0d8716b54f73f96bf50811644a76e5c2 (diff) | |
| download | focaccia-qemu-a3cedb541ca3ecc82040f597a4054419fdb22fa5.tar.gz focaccia-qemu-a3cedb541ca3ecc82040f597a4054419fdb22fa5.zip | |
target-ppc: Use #define instead of opencoding SLB valid bit
Use SLB_ESID_V instead of (1 << 27) in the code Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/mmu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 5dd4e05f78..9c9132ea81 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2061,7 +2061,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) /* ESID = srnum */ rb |= ((uint32_t)srnum & 0xf) << 28; /* Set the valid bit */ - rb |= 1 << 27; + rb |= SLB_ESID_V; /* Index = ESID */ rb |= (uint32_t)srnum; |