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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-17 10:43:46 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-22 14:44:55 +0100 |
| commit | aa5b0b29b12eb5741f0bba01316166d1f721b8f0 (patch) | |
| tree | baf7edccfd67cf24c20c8e070c8b2a9fdf62723e | |
| parent | d9b47e97e76cf439c90df69f0afb710b3bc3cc2c (diff) | |
| download | focaccia-qemu-aa5b0b29b12eb5741f0bba01316166d1f721b8f0.tar.gz focaccia-qemu-aa5b0b29b12eb5741f0bba01316166d1f721b8f0.zip | |
target/arm: Use smin/smax for do_sat_addsub_32
The operation we're performing with the movcond is either min/max depending on cond -- simplify. Use tcg_constant_i64 while we're at it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/translate-sve.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 180e14d9f8..726cf88d7c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1916,8 +1916,6 @@ static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a) static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) { int64_t ibound; - TCGv_i64 bound; - TCGCond cond; /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ if (u) { @@ -1928,15 +1926,12 @@ static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) if (d) { tcg_gen_sub_i64(reg, reg, val); ibound = (u ? 0 : INT32_MIN); - cond = TCG_COND_LT; + tcg_gen_smax_i64(reg, reg, tcg_constant_i64(ibound)); } else { tcg_gen_add_i64(reg, reg, val); ibound = (u ? UINT32_MAX : INT32_MAX); - cond = TCG_COND_GT; + tcg_gen_smin_i64(reg, reg, tcg_constant_i64(ibound)); } - bound = tcg_const_i64(ibound); - tcg_gen_movcond_i64(cond, reg, reg, bound, bound, reg); - tcg_temp_free_i64(bound); } /* Similarly with 64-bit values. */ |