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| author | Max Chou <max.chou@sifive.com> | 2025-04-08 18:39:34 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-05-19 13:39:01 +1000 |
| commit | b5480a693e3e657108746721ffe434b3bb6e7a72 (patch) | |
| tree | 9bcf6c488fc3221af3666fba807fb5120ca91422 | |
| parent | fda68acb7761af40df78db18e44ca1ff20195fe0 (diff) | |
| download | focaccia-qemu-b5480a693e3e657108746721ffe434b3bb6e7a72.tar.gz focaccia-qemu-b5480a693e3e657108746721ffe434b3bb6e7a72.zip | |
target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)
Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard <antonb@tenstorrent.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20250408103938.3623486-7-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Cc: qemu-stable@nongnu.org
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5de50422c9..841692701c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -638,7 +638,9 @@ static bool vext_check_slide(DisasContext *s, int vd, int vs2, { bool ret = require_align(vs2, s->lmul) && require_align(vd, s->lmul) && - require_vm(vm, vd); + require_vm(vm, vd) && + vext_check_input_eew(s, -1, 0, vs2, s->sew, vm); + if (is_over) { ret &= (vd != vs2); } |