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authorJoel Stanley <joel@jms.id.au>2021-11-17 14:57:52 +0800
committerPeter Maydell <peter.maydell@linaro.org>2021-12-15 10:11:34 +0000
commitb662fac6aa800669d3a802f1ddaa1910a42b77ab (patch)
tree6961bbe5d755d4f07c529b289c76abc2504b0cf1
parent9d5dcb8512098ac9dd5ee20f065ac516942d4a26 (diff)
downloadfocaccia-qemu-b662fac6aa800669d3a802f1ddaa1910a42b77ab.tar.gz
focaccia-qemu-b662fac6aa800669d3a802f1ddaa1910a42b77ab.zip
docs: aspeed: ADC is now modelled
Move it to the supported list.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-5-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--docs/system/arm/aspeed.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 6aafd611e9..d8b102fa0a 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -56,13 +56,13 @@ Supported devices
  * Front LEDs (PCA9552 on I2C bus)
  * LPC Peripheral Controller (a subset of subdevices are supported)
  * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA
+ * ADC
 
 
 Missing devices
 ---------------
 
  * Coprocessor support
- * ADC (out of tree implementation)
  * PWM and Fan Controller
  * Slave GPIO Controller
  * Super I/O Controller