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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-02-04 10:26:55 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:25:52 +1000 |
| commit | b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8 (patch) | |
| tree | e921c0f0af88e0e16fe391d4c707cd66893847cc | |
| parent | 05e6ca5e156d1d114d1eb878cae9744cb4a539e3 (diff) | |
| download | focaccia-qemu-b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8.tar.gz focaccia-qemu-b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8.zip | |
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
For non-leaf PTEs, the D, A, and U bits are reserved for future standard use. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu_helper.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7df4569526..25ebc76725 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -937,6 +937,9 @@ restart: return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ + if (pte & (PTE_D | PTE_A | PTE_U)) { + return TRANSLATE_FAIL; + } base = ppn << PGSHIFT; } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { /* Reserved leaf PTE flags: PTE_W */ |